HD6417750RF240DV Datasheet, PDF(45/1132 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

HD6417750RF240DV Datasheet, PDF (45/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

◁

Tables

Section 1 Overview

Table 1.1 LSI Features ................................................................................................................ 1

Table 1.2 Pin Functions............................................................................................................. 14

Table 1.3 Pin Functions............................................................................................................. 24

Table 1.4 Pin Functions............................................................................................................. 32

Table 1.5 Pin Functions............................................................................................................. 42

Section 2 Programming Model

Table 2.1 Initial Register Values............................................................................................... 55

Section 3 Memory Management Unit (MMU)

Table 3.1 MMU Registers......................................................................................................... 74

Section 4 Caches

Table 4.1 Cache Features (SH7750, SH7750S) ...................................................................... 111

Table 4.2 Cache Features (SH7750R) ..................................................................................... 112

Table 4.3 Features of Store Queues......................................................................................... 112

Table 4.4 Cache Control Registers.......................................................................................... 113

Section 5 Exceptions

Table 5.1 Exception-Related Registers ................................................................................... 149

Table 5.2 Exceptions ............................................................................................................... 152

Table 5.3 Types of Reset......................................................................................................... 161

Section 6 Floating-Point Unit (FPU)

Table 6.1 Floating-Point Number Formats and Parameters .................................................... 186

Table 6.2 Floating-Point Ranges ............................................................................................. 187

Table 6.3 Incorrect Operation Result ...................................................................................... 203

Table 6.4 FDIV DRm, DRn (DRn/DRm â DRn) ................................................................. 204

Table 6.5 FADD DRm, DRn (DRn + DRm â DRn) FSUB DRm, DRn

(DRn â DRm â DRn) ............................................................................................ 205

Table 6.6 FMUL DRm, DRn (DRn*DRm â DRn) .............................................................. 205

Table 6.7 TRAP Routine Processing....................................................................................... 207

Section 7 Instruction Set

Table 7.1 Addressing Modes and Effective Addresses ........................................................... 211

Table 7.2 Notation Used in Instruction List ............................................................................ 215

R01UH0456EJ0702 Rev. 7.02

Sep 24, 2013

Page xlv of lii

▷