HD6417750RF240DV Datasheet, PDF (202/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 5 Exceptions
SH7750, SH7750S, SH7750R Group
5.2 Register Descriptions
There are three registers related to exception handling. Addresses are allocated to these registers,
and they can be accessed by specifying the P4 address or area 7 address.
1. The exception event register (EXPEVT) resides at P4 address H'FF00 0024, and contains a 12-
bit exception code. The exception code set in EXPEVT is that for a reset or general exception
event. The exception code is set automatically by hardware when an exception occurs.
EXPEVT can also be modified by software.
2. The interrupt event register (INTEVT) resides at P4 address H'FF00 0028, and contains a 12-
bit exception code. The exception code set in INTEVT is that for an interrupt request. The
exception code is set automatically by hardware when an exception occurs. INTEVT can also
be modified by software.
3. The TRAPA exception register (TRA) resides at P4 address H'FF00 0020, and contains 8-bit
immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when
a TRAPA instruction is executed. TRA can also be modified by software.
The bit configurations of EXPEVT, INTEVT, and TRA are shown in figure 5.1.
EXPEVT and INTEVT
31
0
12 11
0
0
Exception code
TRA
31
0
10 9
2 10
0
imm
00
Legend:
0: Reserved bits. These bits are always read as 0, and should only be written with 0.
imm: 8-bit immediate data of the TRAPA instruction
Figure 5.1 Register Bit Configurations
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Sep 24, 2013