HD6417750RF240DV Datasheet, PDF (429/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 13 Bus State Controller (BSC)
Bits 13 to 11—Area 0 Burst ROM Control (A0BST2–A0BST0): These bits specify whether
burst ROM interface is used in area 0. When burst ROM interface is used, they also specify the
number of accesses in a burst. If area 0 is an MPX interface area, these bits are ignored.
Bit 13: A0BST2 Bit 12: A0BST1 Bit 11: A0BST0 Description
0
0
0
Area 0 is accessed as SRAM interface
(Initial value)
1
Area 0 is accessed as burst ROM
interface (4 consecutive accesses)
Can be used with 8-, 16-, 32-, or 64*-bit
bus width
1
0
Area 0 is accessed as burst ROM
interface (8 consecutive accesses)
Can only be used with 8-, 16-, or 32-bit
bus width
1
Area 0 is accessed as burst ROM
interface (16 consecutive accesses)
Can only be used with 8- or 16-bit bus
width. Do not specify for 32-bit bus width
1
0
0
Area 0 is accessed as burst ROM
interface (32 consecutive accesses)
Can only be used with 8-bit bus width
1
Reserved
1
0
Reserved
1
Reserved
Note: * Settable only for SH7750R.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 377 of 1076