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HD6417750RF240DV Datasheet, PDF (841/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series
SH7750, SH7750S, SH7750R Group
Section 17 Smart Card Interface
Table 17.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
Pck (MHz)
Maximum Bit Rate (bits/s)
N
n
7.1424
19200
0
0
10.00
26882
0
0
10.7136
28800
0
0
16.00
43010
0
0
20.00
53763
0
0
25.0
67204
0
0
30.0
80645
0
0
33.0
88710
0
0
50.0
67204
0
0
The bit rate error is given by the following equation:
Pck
Error (%) = 1488 × 22n – 1 × B × (N + 1) × 106 – 1 × 100
Table 17.8 shows the relationship between the smart card interface transmit/receive clock register
settings and the output state.
Table 17.8 Register Settings and SCK Pin State
Register Values
SCK Pin
Setting SMIF GM CKE1 CKE0 Output
State
1*1
1
0
0
0
Port
Determined by setting of SPB1IO
and SPB1DT bits in SCSPTR1
1
0
0
1
SCK (serial clock) output state
2*2
1
1
0
0
Low output Low-level output state
1
1
0
1
SCK (serial clock) output state
3*2
1
1
1
0
High output High-level output state
1
1
1
1
SCK (serial clock) output state
Notes: 1. The SCK output state changes as soon as the CKE0 bit setting is changed.
Clear the CKE1 bit to 0.
2. Stopping and starting the clock by changing the CKE0 bit setting does not affect the
clock duty cycle.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 789 of 1076