HD6417750RF240DV Datasheet, PDF (524/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
Burst Write: The timing chart for a burst write is shown in figure 13.30. In this LSI, a burst write
occurs only in the event of cache copy-back or a 32-byte transfer by the DMAC. In a burst write
operation, the WRITA command is issued in the Tc1 cycle following the Tr cycle in which the
ACTV command is output. In the write cycle, the write data is output at the same time as the write
command. In the case of the write with auto-precharge command, precharging of the relevant bank
is performed in the synchronous DRAM after completion of the write command, and therefore no
command can be issued for the same bank until precharging is completed. Consequently, in
addition to the precharge wait cycle, Tpc, used in a read access, cycle Trwl is also added as a wait
interval until precharging is started following the write command. Issuance of a new command for
synchronous DRAM is postponed during this interval. The number of Trwl cycles can be specified
by bits TRWL2–TRWL0 in MCR. 32-byte boundary data is written in wraparound mode. DACK
is asserted two cycles before the data write cycle.
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Sep 24, 2013