HD6417750RF240DV Datasheet, PDF (700/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 14 Direct Memory Access Controller (DMAC)
SH7750, SH7750S, SH7750R Group
14.8.3 Transfer Channel Notification in DDT Mode
When the DMAC is set up for four-channel external request acceptance in DDT mode
(DMAOR.DBL = 0), the ID [1:0] bits are used to notify the external device of the DMAC channel
that is to be used. For more details, see section 14.5, On-Demand Data Transfer Mode (DDT
Mode).
When the DMAC is set up for eight-channel external request acceptance in DDT mode
(DMAOR.DBL = 1), the ID [1:0] bits and the simultaneous (on the timing of TDACK assertion)
assertion of ID2 from the BAVL (data bus available) pin are used to notify the external device of
the DMAC channel that is to be used (see table 14.15).
When the DMAC is set up for eight-channel external request acceptance in DDT mode
(DMAOR.DBL = 1), it is important to note that the BAVL pin has the two functions as shown in
table 14.16.
Table 14.15 Notification of Transfer Channel in Eight-Channel DDT Mode
BAVL/ID2
1
0
ID[1:0]
00
01
10
11
00
01
10
11
Transfer Channel
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
Table 14.16 Function of BAVL
TDACK = High
TDACK = Low
Function of BAVL
Bus available
Notification of channel number (ID2)
Page 648 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013