HD6417750RF240DV Datasheet, PDF (536/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
Table 13.17 Cycles for which Pipeline Access is Possible
CPU
Preceding Access
Read Write
CPU
Read
X
X
Write
X
X
DMAC dual
Read
X
X
Write
O
O
DMAC single Read
O
O
Write
O
O
Legend:
O: Pipeline access possible
X: Pipeline access not possible
Succeeding Access
DMAC Dual
Read Write
O
X
O
X
X
X
O
X
X
X
O
X
DMAC Single
Read Write
O
O
O
O
X
X
O
O
O
O
O
O
Refreshing: The bus state controller is provided with a function for controlling synchronous
DRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting
the RFSH bit to 1 in MCR. If synchronous DRAM is not accessed for a long period, self-refresh
mode, in which the power consumption for data retention is low, can be activated by setting both
the RMODE bit and the RFSH bit to 1.
• Auto-Refreshing
Refreshing is performed at intervals determined by the input clock selected by bits CKS2–
CKS0 in RTCSR, and the value set in RTCOR. The value of bits CKS2–CKS0 in RTCOR
should be set so as to satisfy the refresh interval specification for the synchronous DRAM
used. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in MCR,
then make the CKS2–CKS0 setting last of all. When the clock is selected by CKS2–CKS0,
RTCNT starts counting up from the value at that time. The RTCNT value is constantly
compared with the RTCOR value, and if the two values are the same, a refresh request is
generated and an auto-refresh is performed. At the same time, RTCNT is cleared to zero and
the count-up is restarted. Figure 13.40 shows the auto-refresh cycle timing.
First, an REF command is issued in the TRr cycle. After the TRr cycle, new command output
cannot be performed for the duration of the number of cycles specified by bits TRAS2–TRAS0
in MCR plus the number of cycles specified by bits TRC2–TRC0 in MCR. The TRAS2–
TRAS0 and TRC2–TRC0 bits must be set so as to satisfy the synchronous DRAM refresh
cycle time specification (active/active command delay time).
Auto-refreshing is performed in normal operation, in sleep mode, and in the case of a manual
reset.
Page 484 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013