HD6417750RF240DV Datasheet, PDF (23/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

15.2.9 Bit Rate Register (SCBRR1) ................................................................................ 676
15.3 Operation ........................................................................................................................... 684
15.3.1 Overview............................................................................................................... 684
15.3.2 Operation in Asynchronous Mode ........................................................................ 686
15.3.3 Multiprocessor Communication Function............................................................. 698
15.3.4 Operation in Synchronous Mode .......................................................................... 707
15.4 SCI Interrupt Sources and DMAC ..................................................................................... 717
15.5 Usage Notes ....................................................................................................................... 718
Section 16 Serial Communication Interface with FIFO (SCIF) ........................725
16.1 Overview............................................................................................................................ 725
16.1.1 Features................................................................................................................. 725
16.1.2 Block Diagram...................................................................................................... 727
16.1.3 Pin Configuration.................................................................................................. 728
16.1.4 Register Configuration.......................................................................................... 729
16.2 Register Descriptions ......................................................................................................... 729
16.2.1 Receive Shift Register (SCRSR2)......................................................................... 729
16.2.2 Receive FIFO Data Register (SCFRDR2) ............................................................ 730
16.2.3 Transmit Shift Register (SCTSR2) ....................................................................... 730
16.2.4 Transmit FIFO Data Register (SCFTDR2) ........................................................... 731
16.2.5 Serial Mode Register (SCSMR2).......................................................................... 731
16.2.6 Serial Control Register (SCSCR2)........................................................................ 734
16.2.7 Serial Status Register (SCFSR2) .......................................................................... 737
16.2.8 Bit Rate Register (SCBRR2) ................................................................................ 744
16.2.9 FIFO Control Register (SCFCR2) ........................................................................ 745
16.2.10 FIFO Data Count Register (SCFDR2) .................................................................. 749
16.2.11 Serial Port Register (SCSPTR2) ........................................................................... 750
16.2.12 Line Status Register (SCLSR2) ............................................................................ 756
16.3 Operation ........................................................................................................................... 757
16.3.1 Overview............................................................................................................... 757
16.3.2 Serial Operation .................................................................................................... 758
16.4 SCIF Interrupt Sources and the DMAC ............................................................................. 769
16.5 Usage Notes ....................................................................................................................... 770
Section 17 Smart Card Interface ........................................................................775
17.1 Overview............................................................................................................................ 775
17.1.1 Features................................................................................................................. 775
17.1.2 Block Diagram...................................................................................................... 776
17.1.3 Pin Configuration.................................................................................................. 777
17.1.4 Register Configuration.......................................................................................... 777
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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