HD6417750RF240DV Datasheet, PDF (906/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 20 User Break Controller (UBC)
SH7750, SH7750S, SH7750R Group
20.2 Register Descriptions
20.2.1 Access to UBC Control Registers
The access size must be the same as the control register size. If the sizes are different, a write will
not be effected in a UBC register write operation, and a read operation will return an undefined
value. UBC control register contents cannot be transferred to a floating-point register using a
floating-point memory load instruction.
When a UBC control register is updated, use either of the following methods to make the updated
value valid:
1. Execute an RTE instruction after the memory store instruction that updated the register. The
updated value will be valid from the RTE instruction jump destination onward.
2. Execute instructions requiring 5 states for execution after the memory store instruction that
updated the register. As the CPU executes two instructions in parallel and a minimum of 0.5
state is required for execution of one instruction, 11 instructions must be inserted. The updated
value will be valid from the 6th state onward.
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013