HD6417750RF240DV Datasheet, PDF (720/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 15 Serial Communication Interface (SCI)
SH7750, SH7750S, SH7750R Group
Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from
SCTDR1 to SCTSR1 and the next serial transmit data can be written to SCTDR1.
Bit 7: TDRE
0
Description
Valid transmit data has been written to SCTDR1
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When data is written to SCTDR1 by the DMAC
1
There is no valid transmit data in SCTDR1
(Initial value)
[Setting conditions]
• Power-on reset, manual reset, standby mode, or module standby
• When the TE bit in SCSCR1 is 0
• When data is transferred from SCTDR1 to SCTSR1 and data can be
written to SCTDR1
Bit 6—Receive Data Register Full (RDRF): Indicates that the received data has been stored in
SCRDR1.
Bit 6: RDRF
0
Description
There is no valid receive data in SCRDR1
[Clearing conditions]
(Initial value)
• Power-on reset, manual reset, standby mode, or module standby
• When 0 is written to RDRF after reading RDRF = 1
• When data in SCRDR1 is read by the DMAC
1
There is valid receive data in SCRDR1
[Setting condition]
When serial reception ends normally and receive data is transferred from
SCRSR1 to SCRDR1
Note:
SCRDR1 and the RDRF flag are not affected and retain their previous values when an error
is detected during reception or when the RE bit in SCSCR1 is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun
error will occur and the receive data will be lost.
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013