HD6417750RF240DV Datasheet, PDF (348/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 10 Clock Oscillation Circuits
SH7750, SH7750S, SH7750R Group
Bit 10—PLL Circuit 1 Enable (PLL1EN): Specifies whether PLL circuit 1 is on or off.
Bit 10: PLL1EN
0
1
Description
PLL circuit 1 is not used
PLL circuit 1 is used
(Initial value)
Bit 9—PLL Circuit 2 Enable (PLL2EN): Specifies whether PLL circuit 2 is on or off.
Bit 9: PLL2EN
0
1
Description
PLL circuit 2 is not used
PLL circuit 2 is used
(Initial value)
Bits 8 to 6—CPU Clock Frequency Division Ratio (IFC): These bits specify the CPU clock
frequency division ratio with respect to the input clock, 1/2 frequency divider, or PLL circuit 1
output frequency.
Bit 8: IFC2
0
Bit 7: IFC1
0
1
1
0
Other than the above
Bit 6: IFC0
0
1
0
1
0
1
Description
×1
×1/2
×1/3
×1/4
×1/6
×1/8
Setting prohibited (Do not set)
Page 296 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013