HD6417750RF240DV Datasheet, PDF (244/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 6 Floating-Point Unit (FPU)
SH7750, SH7750S, SH7750R Group
• Flag: FPU exception flag field
Cause
Enable
Flag
FPU exception
cause field
FPU exception
enable field
FPU exception
flag field
FPU
Invalid
Division
Error (E) Operation (V) by Zero (Z)
Bit 17
Bit 16
Bit 15
None
Bit 11
Bit 10
None
Bit 6
Bit 5
Overflow Underflow Inexact
(O)
(U)
(I)
Bit 14
Bit 13
Bit 12
Bit 9
Bit 8
Bit 7
Bit 4
Bit 3
Bit 2
When an FPU operation instruction is executed, the FPU exception cause field is cleared to
zero first. When the next FPU exception is occured, the corresponding bits in the FPU
exception cause field and FPU exception flag field are set to 1. The FPU exception flag field
holds the status of the exception generated after the field was last cleared.
• RM: Rounding mode
RM = 00: Round to Nearest
RM = 01: Round to Zero
RM = 10: Reserved
RM = 11: Reserved
• Bits 22 to 31: Reserved
These bits are always read as 0, and should only be written with 0.
6.3.3 Floating-Point Communication Register (FPUL)
Information is transferred between the FPU and CPU via the FPUL register. The 32-bit FPUL
register is a system register, and is accessed from the CPU side by means of LDS and STS
instructions. For example, to convert the integer stored in general register R1 to a single-precision
floating-point number, the processing flow is as follows:
R1 → (LDS instruction) → FPUL → (single-precision FLOAT instruction) → FR1
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013