HD6417750RF240DV Datasheet, PDF (934/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 21 High-performance User Debug Interface (H-UDI)
SH7750, SH7750S, SH7750R Group
The maximum frequency of TCK (TMS, TDI, TDO) is 20 MHz. Make the TCK or CPG setting of
this LSI such that the TCK frequency is lower than that of this LSI’s on-chip peripheral module
clock.
21.1.4 Register Configuration
Table 21.2 shows the H-UDI registers. Except for SDBPR, these registers are mapped in the
control register space and can be referenced by the CPU.
Table 21.2 H-UDI Registers
CPU Side
H-UDI Side
Name
Abbre-
P4
viation R/W Address
Area 7
Address
Access Initial
Access Initial
Size Value^*1 R/W Size Value^*1
Instruction
register
SDIR R H'FFF00000 H'1FF00000 16
H'FFFF R/W 32
H'FFFFFFFD
(Fixed
value^*2)
Data register SDDR/ R/W H'FFF00008 H'1FF00008 32/16 Unde- — —
—
H
SDDRH
fined
Data register SDDRL R/W H'FFF0000A H'1FF0000A 16
Unde- — —
—
L
fined
Bypass
SDBPR — —
—
—
Unde- R/W 1
—
register
fined
Interrupt
source
register^*4
SDINT R/W H'FFF00014 H'1FF00014 16
H'0000 W^*3 32
H'00000000
Boundary
SDBSR — —
—
—
Unde- R/W —
Undefined
scan
fined
register^*4
Notes: 1. Initialized when the TRST pin goes low or when the TAP is in the Test-Logic-Reset
state.
2. The value read from H-UDI is fixed (H'FFFFFFFD).
3. Using the H-UDI interrupt command, a 1 can be written to the least significant bit.
4. SH7750R only
Page 882 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013