HD6417750RF240DV Datasheet, PDF (403/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 12 Timer Unit (TMU)
Example of Count Operation Setting Procedure: Figure 12.2 shows an example of the count
operation setting procedure.
1. Select the count clock, for channel 0, 1, or 2, with bits TPSC2–TPSC0 in the timer control
register (TCR). When an external clock is selected, set the TCLK pin to input mode with the
TCOE bit in TOCR, and select the external clock edge with bits CKEG1 and CKEG0 in TCR.
2. Specify whether an interrupt is to be generated on TCNT underflow with the UNIE bit in TCR.
3. When the input capture function is used, set the ICPE bits in TCR, including specification of
whether the interrupt function is to be used.
4. Set a value in the timer constant register (TCOR).
5. Set the initial value in the timer counter (TCNT).
6. Set the STR bit to 1 in the timer start register (TSTR, TSTR2) to start the count.
Operation selection
Select count clock ₁
Underflow interrupt
generation setting
2
When input capture
function is used
Input capture interrupt ₃
generation setting
Timer constant
register setting
4
Set initial timer
counter value
5
Start count
6
Note: When an interrupt is generated, clear the source flag in the interrupt handler. If the interrupt
enabled state is set without clearing the flag, another interrupt will be generated.
Figure 12.2 Example of Count Operation Setting Procedure
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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