HD6417750RF240DV Datasheet, PDF (498/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
Read-Strobe Negate Timing (Setting Only Possible in the SH7750R): When the SRAM
interface is used, timing for the negation of the strobe during read operations can be specified by
the setting of the A1RDH and A4RDH bits of the WCR3 register. For information about this
setting, see the description of the WCR3 register. When a byte control SRAM setting is made,
AnRDH should be cleared to 0.
TS1 T1 Tw Tw Tw Tw T2 TH1 TH2
CKIO
A25−A0
CSn
RD/WR
*
RD
D63−D0
BS
TS1: Setup wait
WCR3.AnS
(0 to 1)
Tw: Access wait
WCR2.AnW
(0 to 15)
TH1, TH2: Hold wait
WCR3.AnH
(0 to 3)
Note: * When AnRDH is set to 1
Figure 13.13 SRAM Interface Read-Strobe Negate Timing (AnS = 1, AnW = 4, AnH = 2)
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Sep 24, 2013