HD6417750RF240DV Datasheet, PDF (491/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 13 Bus State Controller (BSC)
CKIO
A25–A0
CSn
RD/WR
RD
D63–D0
(read)
WEn
D63–D0
(write)
BS
T1
T2
RDY
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
DACKn
(DA)
Legend:
SA: Single address DMA
DA: Dual address DMA
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.6 Basic Timing of SRAM Interface
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 439 of 1076