HD6417750RF240DV Datasheet, PDF (142/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 3 Memory Management Unit (MMU)
SH7750, SH7750S, SH7750R Group
3.4.2 Instruction TLB (ITLB) Configuration
The ITLB is used to translate a virtual address to a physical address in an instruction access.
Information in the address translation table located in the UTLB is cached into the ITLB. Figure
3.9 shows the overall configuration of the ITLB. The ITLB consists of 4 fully-associative type
entries. The address translation information is almost the same as that in the UTLB, but with the
following differences:
1. D and WT bits are not supported.
2. There is only one PR bit, corresponding to the upper of the PR bits in the UTLB.
Entry 0 ASID [7:0] VPN [31:10] V
Entry 1 ASID [7:0] VPN [31:10] V
Entry 2 ASID [7:0] VPN [31:10] V
Entry 3 ASID [7:0] VPN [31:10] V
PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC
PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC
PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC
PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC
Figure 3.9 ITLB Configuration
3.4.3 Address Translation Method
Figures 3.10 and 3.11 show flowcharts of memory accesses using the UTLB and ITLB.
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Sep 24, 2013