HD6417750RF240DV Datasheet, PDF (174/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 4 Caches
SH7750, SH7750S, SH7750R Group
3e. Cache miss (with copy-back/write-back)
The tag and data field of the cache line indexed by effective address bits [13:5] are first saved
in the write-back buffer, and then a data write in accordance with the access size
(quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective
address of the data field of the cache line indexed by effective address bits [13:5]. Then, data is
read into the cache line from the external memory space corresponding to the effective
address. Data reading is performed, using the wraparound method, in order from the longword
data corresponding to the effective address, and one cache line of data is read excluding the
written data. During this time, the CPU can execute the next processing. When reading of one
line of data is completed, the tag corresponding to the effective address is recorded in the
cache, and 1 is written to the V bit and U bit. The data in the write-back buffer is then written
back to external memory.
4.3.4 Write-Back Buffer
In order to give priority to data reads to the cache and improve performance, this LSI has a write-
back buffer which holds the relevant cache entry when it becomes necessary to purge a dirty cache
entry into external memory as the result of a cache miss. The write-back buffer contains one cache
line of data and the physical address of the purge destination.
Physical address bits [28:5] LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7
Figure 4.4 Configuration of Write-Back Buffer
4.3.5 Write-Through Buffer
This LSI has a 64-bit buffer for holding write data when writing data in write-through mode or
writing to a non-cacheable area. This allows the CPU to proceed to the next operation as soon as
the write to the write-through buffer is completed, without waiting for completion of the write to
external memory.
Physical address bits [28:0] LW0 LW1
Figure 4.5 Configuration of Write-Through Buffer
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Sep 24, 2013