HD6417750RF240DV Datasheet, PDF (818/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
SH7750, SH7750S, SH7750R Group
Error handling
No
ORER = 1?
Yes
Overrun error handling
No
ER = 1?
Yes
Receive error handling
1. Whether a framing error or parity error
has occurred that is to be read from
SCFRDR2 can be ascertained from
the FER and PER bits in SCFSR2.
2. When a break signal is received,
receive data is not transferred to
SCFRDR2 while the BRK flag is set.
However, note that the last data in
SCFRDR2 is H'00 (the break data in
which a framing error occurred is
stored).
No
BRK = 1?
Yes
Break handling
No
DR = 1?
Yes
Read receive data in SCFRDR2
Clear DR, ER, BRK flags
in SCFSR2,
and ORER flag in SCLSR2, to 0
End
Figure 16.10 Sample Serial Reception Flowchart (2)
Page 766 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013