HD6417750RF240DV Datasheet, PDF (839/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 17 Smart Card Interface
Inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit
inversion, the O/E bit in SCSMR1 is set to odd parity mode. (This applies to both transmission and
reception).
(Z)
A Z Z A Z Z Z A A Z (Z) State
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(a) Direct convention (SDIR = SINV = O/E = 0)
(Z)
A Z Z A A A A A A Z (Z) State
Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp
(b) Inverse convention (SDIR = SINV = O/E = 1)
Figure 17.5 Sample Start Character Waveforms
17.3.5 Clock
Only an internal clock generated by the on-chip baud rate generator can be used as the
transmit/receive clock for the smart card interface. The bit rate is set with the bit rate register
(SCBRR1) and the CKS1 and CKS0 bits in the serial mode register (SCSMR1). The equation for
calculating the bit rate is shown below. Table 17.5 shows some sample bit rates.
If clock output is selected with CKE0 set to 1, a clock with a frequency of 372 times the bit rate is
output from the SCK pin.
B
=
1488
×
Pck
2^{2n – 1}
×
(N
+
1)
×
10⁶
Where: N = Value set in SCBRR1 (0 ≤ N ≤ 255)
B = Bit rate (bits/s)
Pck = Peripheral module operating frequency (MHz)
n = 0 to 3 (See table 17.4)
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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