HD6417750RF240DV Datasheet, PDF (909/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 20 User Break Controller (UBC)
Bits 3, 1, and 0—Break Address Mask A2 to A0 (BAMA2–BAMA0): These bits specify which
bits of the channel A break address 31 to 0 (BAA31–BAA0) set in BARA are to be masked.
Bit 3: BAMA2 Bit 1: BAMA1
0
0
1
1
0
1
Legend: *: Don't care
Bit 0: BAMA0
0
1
0
1
0
1
*
Description
All BARA bits are included in break
conditions
Lower 10 bits of BARA are masked, and not
included in break conditions
Lower 12 bits of BARA are masked, and not
included in break conditions
All BARA bits are masked, and not included
in break conditions
Lower 16 bits of BARA are masked, and not
included in break conditions
Lower 20 bits of BARA are masked, and not
included in break conditions
Reserved (cannot be set)
20.2.5 Break Bus Cycle Register A (BBRA)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
—
Initial value: 0
R/W: R
6
SZA2
0
R/W
5
IDA1
0
R/W
4
IDA0
0
R/W
3
RWA1
0
R/W
2
RWA0
0
R/W
1
SZA1
0
R/W
0
SZA0
0
R/W
Break bus cycle register A (BBRA) is a 16-bit readable/writable register that sets three
conditions—(1) instruction access/operand access, (2) read/write, and (3) operand size—from
among the channel A break conditions.
BBRA is initialized to H'0000 by a power-on reset. It retains its value in standby mode.
Bits 15 to 7—Reserved: These bits are always read as 0, and should only be written with 0.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 857 of 1076