HD6417750RF240DV Datasheet, PDF (528/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
different area during this time has no effect. If there is an access to a different row address in the
bank active state, after this is detected the bus cycle in figure 13.34 or 13.37 is executed instead of
that in figure 13.33 or 13.36. In RAS down mode, too, a PALL command is issued before a refresh
cycle or before bus release due to bus arbitration.
CKIO
Bank
Tr Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4
Row
Precharge-sel
Row
H/L
Address
Row
c1
CSn
RD/WR
RAS
CASS
DQMn
D63–D0
(read)
c1 c2 c3 c4
BS
CKE
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.32 Burst Read Timing
Page 476 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013