HD6417750RF240DV Datasheet, PDF (443/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 13 Bus State Controller (BSC)
13.2.6 Wait Control Register 2 (WCR2)
Wait control register 2 (WCR2) is a 32-bit readable/writable register that specifies the number of
wait states to be inserted for each area. It also specifies the data access pitch when performing
burst memory access. This enables low-speed memory to be connected without using external
circuitry.
WCR2 is initialized to H'FFFEEFFF by a power-on reset, but is not initialized by a manual reset
or in standby mode.
Bit: 31
A6W2
Initial value: 1
R/W: R/W
30
A6W1
1
R/W
29
A6W0
1
R/W
28
A6B2
1
R/W
27
A6B1
1
R/W
26
A6B0
1
R/W
25
A5W2
1
R/W
24
A5W1
1
R/W
Bit: 23
22
21
20
19
18
17
16
A5W0 A5B2 A5B1 A5B0 A4W2 A4W1 A4W0 —
Initial value: 1
1
1
1
1
1
1
0
R/W: R/W R/W R/W R/W R/W R/W R/W
R
Bit: 15
14
13
12
11
10
9
8
A3W2 A3W1 A3W0 — A2W2 A2W1 A2W0 A1W2
Initial value: 1
1
1
0
1
1
1
1
R/W: R/W R/W R/W
R
R/W R/W R/W R/W
Bit:
Initial value:
R/W:
7
A1W1
1
R/W
6
A1W0
1
R/W
5
A0W2
1
R/W
4
A0W1
1
R/W
3
A0W0
1
R/W
2
A0B2
1
R/W
1
A0B1
1
R/W
0
A0B0
1
R/W
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 391 of 1076