HD6417750RF240DV Datasheet, PDF (683/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 14 Direct Memory Access Controller (DMAC)
Four requests can be queued
CLK
1st 2nd 3rd 4th
5th
DBREQ
BAVL
TR
Handshaking is necessary
to send additional requests
A25–A0
D63–D0
RAS,
CAS, WE
TDACK
ID1, ID0
CA
CA
CA
CA
D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3
WT
WT
WT
WT
Must be ignored
(no request transmitted)
Figure 14.52 Single Address Mode/Burst Mode/External Device → External Bus Data
Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2
14.5.4 Notes on Use of DDT Module
1. Normal data transfer mode (channel 0)
Initial settings for channel 0 demand transfer must be DTR.ID = 00 and DTR.MD = 01, 10, or
11. In this case, only single address mode can be set for channel 0.
2. Normal data transfer mode (channels 1 to 3)
If a setting of DTR.ID = 01, 10, or 11 is made, DTR.MD will be ignored.
3. Handshake protocol using the data bus (valid on channel 0 only)
a. The handshake protocol using the data bus can be executed only on channel 0. (Set
DTR.ID = 00, DTR.MD = 00, DTR.SZ ≠ 101 or 110. Operation is not guaranteed if
settings of DTR.ID = 00, DTR.MD = 00, and DTR.SZ = 101 or 110 are made.)
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 631 of 1076