HD6417750RF240DV Datasheet, PDF (762/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 15 Serial Communication Interface (SCI)
SH7750, SH7750S, SH7750R Group
Serial Data Transmission (Synchronous Mode): Figure 15.19 shows a sample flowchart for
serial transmission.
Use the following procedure for serial data transmission after enabling the SCI for transmission.
Start of transmission
Read TDRE flag in SCSSR1
No
TDRE = 1?
Yes
Write transmit data to SCTDR1
and clear TDRE flag
in SCSSR1 to 0
No
All data transmitted?
Yes
1. SCI status check and transmit
data write: Read SCSSR1 and
check that the TDRE flag is set to
1, then write transmit data to
SCTDR1 and clear the TDRE flag
to 0.
2. To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
possible, then write data to
SCTDR1, and then clear the
TDRE flag to 0. (Checking and
clearing of the TDRE flag is
automatic when the direct
memory access controller
(DMAC) is activated by a
transmit-data-empty interrupt
(TXI) request, and data is written
to SCTDR1.)
Read TEND flag in SCSSR1
No
TEND = 1?
Yes
Clear TE bit in SCSCR1 to 0
End
Figure 15.19 Sample Serial Transmission Flowchart
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013