HD6417750RF240DV Datasheet, PDF (1060/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 22 Electrical Characteristics
SH7750, SH7750S, SH7750R Group
Table 22.40 Peripheral Module Signal Timing (4)
HD6417750
VF128 (V)
*²
Module Item
Symbol Min Max
TMU,
RTC
Timer clock
pulse width
(high)
Timer clock
pulse width
(low)
Timer clock
rise time
t
TCLKWH
t
TCLKWL
t
TCLKr
4
—
4
—
— 0.8
Timer clock
t
TCLKf
fall time
Oscillation
t_ROSC
settling time
SCI
Input clock t
Scyc
cycle (asyn-
chronous)
Input clock
t_Scyc
cycle (syn-
chronous)
Input clock
t
SCKW
pulse width
Input clock t
SCKr
rise time
Input clock fall t
SCKf
time
— 0.8
—3
4
—
6
—
0.4 0.6
— 0.8
— 0.8
Transfer data t
TXD
delay time
Receive data t
RXS
setup time
(synchronous)
1.3 10
16 —
I/O
ports
Receive data t
RXH
hold time
(synchronous)
Output data
delay time
t_PORTD
Input data
setup time
t
PORTS
Input data hold t
PORTH
time
16 —
0.5 10
3.5 —
1.5 —
HD6417750
F167 (V)
*³
Min Max
4
—
4
—
— 0.8
— 0.8
—3
4
—
6
—
0.4 0.6
— 0.8
— 0.8
1.3 8
16 —
16 —
0.5 8
3.5 —
1.5 —
HD6417750
BP200M (V)
*⁴
Min Max Unit Figure
4
— Pcyc^*1 22.61
4
— Pcyc^*1 22.61
— 0.8 Pcyc^*1 22.61
— 0.8 Pcyc^*1 22.61
—3
s
22.62
4
— Pcyc^*1 22.63
6
— Pcyc^*1 22.63
0.4 0.6 t
Scyc
22.63
— 0.8 Pcyc^*1 22.63
— 0.8 Pcyc^*1 22.63
1.2 6
ns
22.64
16 — ns
22.64
16 — ns
22.64
0.5 6
ns
3
— ns
1.5 — ns
22.65
22.65
22.65
Page 1008 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013