HD6417750RF240DV Datasheet, PDF (204/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 5 Exceptions
SH7750, SH7750S, SH7750R Group
5.4 Exception Types and Priorities
Table 5.2 shows the types of exceptions, with their relative priorities, vector addresses, and
exception/interrupt codes.
Table 5.2 Exceptions
Exception Execution
Category Mode
Exception
Priority Priority Vector
Level Order Address
Offset
Reset
Abort type Power-on reset
1
1
H'A000 0000 —
Manual reset
1
2
H'A000 0000 —
H-UDI reset
1
1
H'A000 0000 —
Instruction TLB multiple-hit
1
3
H'A000 0000 —
exception
Data TLB multiple-hit exception 1
4
H'A000 0000 —
General Re-
User break before instruction 2
0
(VBR/DBR) H'100/
exception execution execution^*1
—
type
Instruction address error
2
1
(VBR)
H'100
Instruction TLB miss exception 2
2
(VBR)
H'400
Instruction TLB protection
2
violation exception
3
(VBR)
H'100
General illegal instruction
2
exception
4
(VBR)
H'100
Slot illegal instruction exception 2
4
(VBR)
H'100
General FPU disable exception 2
4
(VBR)
H'100
Slot FPU disable exception
2
4
(VBR)
H'100
Data address error (read)
2
5
(VBR)
H'100
Data address error (write)
2
5
(VBR)
H'100
Data TLB miss exception (read) 2
6
(VBR)
H'400
Data TLB miss exception (write) 2
6
(VBR)
H'400
Data TLB protection
2
violation exception (read)
7
(VBR)
H'100
Data TLB protection
2
violation exception (write)
7
(VBR)
H'100
FPU exception
2
8
(VBR)
H'100
Initial page write exception
2
9
(VBR)
H'100
Completion Unconditional trap (TRAPA) 2
type
User break after instruction
2
execution^*1
4
(VBR)
H'100
10
(VBR/DBR) H'100/
—
Exception
Code
H'000
H'020
H'000
H'140
H'140
H'1E0
H'0E0
H'040
H'0A0
H'180
H'1A0
H'800
H'820
H'0E0
H'100
H'040
H'060
H'0A0
H'0C0
H'120
H'080
H'160
H'1E0
Page 152 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013