HD6417750RF240DV Datasheet, PDF (361/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 10 Clock Oscillation Circuits
10.11 Usage Notes
10.11.1 Invalid Manual Reset Triggered by Watchdog Timer (SH7750 and SH7750S)
Under certain conditions the watchdog timer (WDT) may trigger an invalid manual reset.
Conditions Under which Problem Occurs: The internal WDT triggers an invalid manual reset
when all of the following four conditions are satisfied.
1. After the WDT overflows, regardless of the values of the WT/IT and RSTS bits in WTCSR.
2. Before the counter (WTCNT) is incremented by the clock specified by the WTCSR.CKS bit.
3. The value of at least one of the TME, WT/IT, and RSTS bits in WTCSR is 0.
4. A value of 1 is written to the TME, WT/IT, and RSTS bits in WTCSR.
Workaround: A workaround for this problem is to use software to increment WTCNT before
writing 1 to the TME, WT/IT, and RSTS bits in WTCSR. Specific lines of code for this purpose
are listed below.
Example: Add the following lines of code before the instructions for writing 1 to the TME,
WT/IT, and RSTS bits in WTCSR.
MOV.L #WTCNT,R7
MOV.W #H'5A00,R8
MOV.W R8,@R7
MOV.L #WTCSR,R9
MOV.W #H'A580,R10
MOV.W R10,@R9
LOOP_WDT:
MOV.B @R7,R0
CMP/EQ #H'00, R0
BT
LOOP_WDT
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 309 of 1076