HD6417750RF240DV Datasheet, PDF (584/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
CKIO
T1
Tw
T2
A25–A0
CSn
RD/WR
RD
D63–D0
(read)
WEn
BS
RDY
DACKn
(SA: IO ← memory)
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.76 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle)
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013