HD6417750RF240DV Datasheet, PDF (467/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 13 Bus State Controller (BSC)
BL
000: Reserved
001: Reserved
010: 4
011: 8
100: Reserved
101: Reserved
110: Reserved
111: Reserved
LMODE
000: Reserved
001: 1
010: 2
011: 3
100: Reserved
101: Reserved
110: Reserved
111: Reserved
Note: * SH7750R only.
13.2.11 Refresh Timer Control/Status Register (RTCSR)
The refresh timer control/status register (RTCSR) is a 16-bit readable/writable register that
specifies the refresh cycle and whether interrupts are to be generated.
RTCSR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in
standby mode.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: —
—
—
—
—
—
—
—
Bit:
Initial value:
R/W:
7
CMF
0
R/W
6
CMIE
0
R/W
5
CKS2
0
R/W
4
CKS1
0
R/W
3
CKS0
0
R/W
2
OVF
0
R/W
1
OVIE
0
R/W
0
LMTS
0
R/W
Bits 15 to 8—Reserved: These bits are always read as 0. For the write values, see section 13.2.15,
Notes on Accessing Refresh Control Registers.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 415 of 1076