HD6417750RF240DV Datasheet, PDF (598/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 14 Direct Memory Access Controller (DMAC)
SH7750, SH7750S, SH7750R Group
• Transfer requests: The following three DMAC transfer activation requests are supported.
⎯ External request
(1) Normal DMA mode
From two DREQ pins. Either low level detection or falling edge detection can be
specified. External requests can be accepted on channels 0 and 1 only.
(2) On-demand data transfer mode (DDT mode)
In this mode of the SH7750 and SH7750S, interfacing between an external device and
the DMAC is performed using the DBREQ, BAVL, TR, TDACK, ID [1:0], and D
[63:0] pins. External requests can be accepted on all four channels.
In the SH7750R, the DBREQ, BAVL, TR, TDACK, ID [2:0], and D [63:0] pins are
used as the interface between an external device and the DMAC. External requests can
be accepted on any of the eight channels.
For channel 0, data transfer can be carried out with the transfer mode, number of
transfers, transfer address (single only), etc., specified by the external device.
Although channel 0 has no request queue, there are four request queues for each of the
other channels: i.e., channels 1 to 3 in the SH7750 or SH7750S, and channels 1 to 7 in
the SH7750R.
In the SH7750R, request queues can be cleared on a channel-by-channel basis in DDT
mode in either of the following two ways.
• Clearing a request queue by DTR format
The request queues of the relevant channel are cleared when it receives DTR.SZ =
110, DTR.ID = 00, DTR.MD = 11, and DTR.COUNT [7:4]* = [1−8].
• Using software to clear the request queue
The request queues of the relevant channel are cleared by writing a 1 to the
CHCRn.QCL bit (request-queue clear bit) of each channel.
Note: * DTR.COUNT [7:4] (DTR [55:52]): Sets the port as not used.
⎯ Requests from on-chip peripheral modules
Transfer requests from the SCI, SCIF, and TMU. These can be accepted on all channels.
⎯ Auto-request
The transfer request is generated automatically within the DMAC.
• Channel functions: Transfer modes that can be set are different for each channel.
⎯ Normal DMA mode
• Channel 0: Single or dual address mode. External requests are accepted.
• Channel 1: Single or dual address mode. External requests are accepted.
• Channel 2: Dual address mode only.
• Channel 3: Dual address mode only.
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013