HD6417750RF240DV Datasheet, PDF (464/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
Bits 2 to 0—OE/WE Negation-Address Delay (A6TEH2–A6TEH0): These bits set the address
hold delay time from OE/WE negation in a write on the connected PCMCIA interface or in an I/O
card read. In the case of a memory card read, the address hold delay time from the data sampling
timing is set. The setting of these bits is selected when the PCMCIA interface access TC bit is set
to 1.
Bit 2: A6TEH2
0
1
Bit 1: A6TEH1
0
1
0
1
Bit 0: A6TEH0
0
1
0
1
0
1
0
1
Waits Inserted
0 (Initial value)
1
2
3
6
9
12
15
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013