HD6417750RF240DV Datasheet, PDF (891/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 19 Interrupt Controller (INTC)
19.3.3 Interrupt-Priority-Level Setting Register 00 (INTPRI00) (SH7750R Only)
The interrupt-priority-level setting register 00 (INTPRI00) sets the priority levels (levels 15−0) for
the on-chip peripheral module interrupts. INTPRI00 is a 32-bit readable/writable register. It is
initialized to H'00000000 by a reset, but is not initialized when the device enters standby mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R
Table 19.7 shows the correspondence between interrupt request sources and the bits in INTPRI00.
Table 19.7 Interrupt Request Sources and the Bits of the INTPRI00 Register
Bit
Register 31 to 28 27 to 24 23 to 20 19 to 16 15 to 12 11 to 8 7 to 4
3 to 0
Interrupt- Reserved
priority-level
setting
register 00
Reserved
Reserved
Reserved
TMU ch4 TMU ch3 Reserved
Reserved
Note:
As shown in the table above, levels for all eight on-chip peripheral modules are assigned in
a single register. The interrupt priority level for the interrupt source that corresponds to each
set of four bits is set as a value from H'F (1111) to H'0 (0000). The setting H'F selects
interrupt priority level 15, which is the highest, and H'0 selects level 0, which means that
interrupt requests from that source are masked.
Reserved bits are always read as 0. When writing, only 0s should be written to these bits.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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