HD6417750RF240DV Datasheet, PDF (312/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 9 Power-Down Modes
SH7750, SH7750S, SH7750R Group
Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes
Status
Power-
Down
Mode
Entering
Conditions CPG
CPU
On-Chip
Memory
On-chip
Peripheral
Modules Pins
External Exiting
Memory Method
Sleep
SLEEP
instruction
executed
while STBY
bit is 0 in
STBCR
Operating
Halted
(registers
held)
Held
Deep sleep SLEEP
instruction
executed
while STBY
bit is 0 in
STBCR,
and DSLP
bit is 1 in
STBCR2
Operating
Halted
(registers
held)
Held
Operating Held
Operating Held
(DMA
halted)
Refreshing • Interrupt
• Reset
Self-
• Interrupt
refreshing _{• Reset}
Standby
SLEEP
Halted
instruction
executed
while STBY
bit is 1 in
STBCR
Halted Held
(registers
held)
Halted* Held
Self-
• Interrupt
refreshing _{• Reset}
Hardware Setting CA
standby pin low
(SH7750S,
SH7750R)
Halted
Halted
Undefined Halted*
High
Undefined ^{• Power-on}
impedance
reset
Module
standby
Setting
MSTP bit
to 1 in
STBCR/
STBCR2
Operating Operating Held
Specified
modules
halted*
Held
Refreshing ^{• Clearing}
MSTP bit
to 0
• Reset
Note: * The RTC operates when the START bit in RCR2 is 1 (see section 11, Realtime Clock
(RTC)).
Page 260 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013