HD6417750RF240DV Datasheet, PDF (399/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 12 Timer Unit (TMU)
Bits 15 to 9, 7, and 6 (Channels 0 and 1); Bits 15 to 10 (Channel 2)—Reserved: These bits are
always read as 0. A write to these bits is invalid, but the write value should always be 0.
Bit 9—Input Capture Interrupt Flag (ICPF) (Channel 2 Only): Status flag, provided in
channel 2 only, that indicates the occurrence of input capture.
Bit 9: ICPF
Description
0
Input capture has not occurred
[Clearing condition]
When 0 is written to ICPF
1
Input capture has occurred
[Setting condition]
When input capture occurs*
Note: * Writing 1 does not change the value.
(Initial value)
Bit 8—Underflow Flag (UNF): Status flag that indicates the occurrence of underflow.
Bit 8: UNF
Description
0
TCNT has not underflowed
[Clearing condition]
When 0 is written to UNF
1
TCNT has underflowed
[Setting condition]
When TCNT underflows*
Note: * Writing 1 does not change the value.
(Initial value)
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 347 of 1076