HD6417750RF240DV Datasheet, PDF (509/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 13 Bus State Controller (BSC)
CKIO
A25–A0
Tpc Tr1 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2
r
c1
c2
c3
c4
CSn
RD/WR
RAS
CAS
D63–D0
(read)
D63–D0
(write)
d1
d2
d3
d4
d1
d2
d3
d4
BS
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.22 (1) DRAM Burst Bus Cycle, RAS Down Mode Start
(Fast Page Mode, RCD = 0, AnW = 0)
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 457 of 1076