HD6417750RF240DV Datasheet, PDF (508/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
CKIO
A25–A0
CSn
RD/WR
RAS
CAS
D63–D0
(read)
Tr1 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tce Tpc
r
c1
c2
c3
c4
d1
d2
d3
d4
BS
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.21 Burst Access Timing in DRAM EDO Mode
RAS Down Mode: This LSI has an address comparator for detecting row address matches in burst
mode. By using this address comparator, and also setting RAS down mode specification bit RASD
to 1, it is possible to select RAS down mode, in which RAS remains asserted after the end of an
access. When RAS down mode is used, if the refresh cycle is longer than the maximum DRAM
RAS assert time, the refresh cycle must be decreased to or below the maximum value of t_RAS.
RAS down mode can only be used when DRAM is connected in area 3.
In RAS down mode, in the event of an access to an address with a different row address, an access
to a different area, a refresh request, or a bus request, RAS is negated and the necessary operation
is performed. When DRAM access is resumed after this, since this is the start of RAS down mode,
the operation starts with row address output. Timing charts are shown in figures 13.22 (1) to (4).
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013