HD6417750RF240DV Datasheet, PDF (707/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 15 Serial Communication Interface (SCI)
Section 15 Serial Communication Interface (SCI)
15.1 Overview
This LSI is equipped with a single-channel serial communication interface (SCI) and a single-
channel serial communication interface with built-in FIFO registers (SCI with FIFO: SCIF).
The SCI can handle both asynchronous and synchronous serial communication.
The SCI supports a smart card interface. This is a serial communication function supporting a
subset of the ISO/IEC 7816-3 (identification cards) standard. For details, see section 17, Smart
Card Interface.
The SCIF is a dedicated asynchronous communication serial interface with built-in 16-stage FIFO
registers for both transmission and reception. For details, see section 16, Serial Communication
Interface with FIFO (SCIF).
15.1.1 Features
SCI features are listed below.
• Choice of synchronous or asynchronous serial communication mode
⎯ Asynchronous mode
Serial data communication is executed using an asynchronous system in which
synchronization is achieved character by character. Serial data communication can be
carried out with standard asynchronous communication chips such as a Universal
Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface
Adapter (ACIA). A multiprocessor communication function is also provided that enables
serial data communication with a number of processors.
There is a choice of 12 serial data transfer formats.
Data length:
7 or 8 bits
Stop bit length:
1 or 2 bits
Parity:
Even/odd/none
Multiprocessor bit:
1 or 0
Receive error detection: Parity, overrun, and framing errors
Break detection:
A break can be detected by reading the RxD pin level directly
from the serial port register (SCSPTR1) when a framing error
occurs.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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