HD6417750RF240DV Datasheet, PDF (526/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
interval. The number of Trwl cycles can be specified by bits TRWL2–TRWL0 in MCR. DACK is
asserted two cycles before the data write cycle.
As this LSI supports burst read/burst write operations for synchronous DRAM, there are empty
cycles in a single write operation.
CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
Tr Trw Tc1 Tc2 Tc3 Tc4 Trwl Trwl Tpc
Row
Row
H/L
Row
c1
CASS
DQMn
D63–D0
c1
(read)
BS
CKE
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.31 Basic Timing for Synchronous DRAM Single Write
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013