HD6417750RF240DV Datasheet, PDF (922/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 20 User Break Controller (UBC)
SH7750, SH7750S, SH7750R Group
2. Instruction access match on channel A, operand access match on channel B
Instruction B is 0 or 1 instruction after Sequential operation is not guaranteed.
instruction A
Instruction B is 2 or more instructions Sequential operation is guaranteed.
after instruction A
3. Operand access match on channel A, instruction access match on channel B
Instruction B is 0 to 3 instructions after Sequential operation is not guaranteed.
instruction A
Instruction B is 4 or more instructions Sequential operation is guaranteed.
after instruction A
4. Operand access matches on both channel A and channel B
Do not make a setting such that a single operand access will match the break conditions of
both channel A and channel B. There are no other restrictions. For example, sequential
operation is guaranteed even if two accesses within a single instruction match channel A and
channel B conditions in turn.
20.3.9 Usage Notes
1. Do not execute a post-execution instruction access break for the SLEEP instruction.
2. Do not make an operand access break setting between 1 and 3 instructions before a SLEEP
instruction.
3. The value of the BL bit referenced in a user break exception depends on the break setting, as
follows.
a. Pre-execution instruction access break: The BL bit value before the executed instruction is
referenced.
b. Post-execution instruction access break: The OR of the BL bit values before and after the
executed instruction is referenced.
c. Operand access break (address/data): The BL bit value after the executed instruction is
referenced.
d. In the case of an instruction that modifies the BL bit
Page 870 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013