HD6417750RF240DV Datasheet, PDF (698/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 14 Direct Memory Access Controller (DMAC)
SH7750, SH7750S, SH7750R Group
Table 14.14 Channel Selection by DTR Format (DMAOR.DBL = 1)
DTR.ID[1:0]
00
01
10
11
DTR.SZ[2:0] ≠ 101
CH0
CH1
CH2
CH3
DTR.SZ[2:0] = 101
CH4
CH5
CH6
CH7
63 61 60 59 58 57 56 55
48 47
32 31
0
SZ R/W ID MD COUNT (Reserved)
ADDRESS
Figure 14.54 DTR Format (Transfer Request Format) (SH7750R)
Bits 13 to 10—Reserved: These bits are always read as 0, and should only be written with 0.
Bits 9 and 8—Priority Mode 1 and 0 (PR1, PR0): These bits determine the order of priority for
channel execution when transfer requests are made for a number of channels simultaneously.
DMAOR
Bit 9
PR1
0
0
1
1
DMAOR
Bit 8
PR0
0
1
0
1
Description
CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7
CH0 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 > CH1
CH2 > CH0 > CH1 > CH3 > CH4 > CH5 > CH6 > CH7
Round robin mode
(Initial value)
Bits 7 to 3—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 2—Address Error Flag (AE): Indicates that an address error has occurred during DMA
transfer. If this bit is set during data transfer, transfers on all channels are suspended, and an
interrupt request (DMAE) is generated. The CPU cannot write 1 to AE. This bit can only be
cleared by writing 0 after reading 1. For details of the settings, see the description of the AE bit in
section 14.2.5, DMA Operation Register (DMAOR)
Bit 1—NMI Flag (NMIF): Indicates that NMI has been input. This bit is set regardless of
whether or not the DMAC is operating. If this bit is set during data transfer, transfers on all
channels are suspended. The CPU cannot write 1 to NMIF. This bit can only be cleared by writing
0 after reading 1. For details of the settings, see the description of the NMIF bit in section 14.2.5,
DMA Operation Register (DMAOR)
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013