HD6417750RF240DV Datasheet, PDF (782/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
SH7750, SH7750S, SH7750R Group
SCRSR2 cannot be directly read or written to by the CPU.
16.2.2 Receive FIFO Data Register (SCFRDR2)
Bit: 7
6
5
4
3
2
1
0
R/W: R
R
R
R
R
R
R
R
SCFRDR2 is a 16-stage FIFO register that stores received serial data.
When the SCIF has received one byte of serial data, it transfers the received data from SCRSR2 to
SCFRDR2 where it is stored, and completes the receive operation. SCRSR2 is then enabled for
reception, and consecutive receive operations can be performed until the receive FIFO register is
full (16 data bytes).
SCFRDR2 is a read-only register, and cannot be written to by the CPU.
If a read is performed when there is no receive data in the receive FIFO register, an undefined
value will be returned. When the receive FIFO register is full of receive data, subsequent serial
data is lost.
The contents of SCFRDR2 are undefined after a power-on reset or manual reset.
16.2.3 Transmit Shift Register (SCTSR2)
Bit: 7
6
5
4
3
2
1
0
R/W: —
—
—
—
—
—
—
—
SCTSR2 is the register used to transmit serial data.
To perform serial data transmission, the SCIF first transfers transmit data from SCFTDR2 to
SCTSR2, then sends the data to the TxD2 pin starting with the LSB (bit 0).
When transmission of one byte is completed, the next transmit data is transferred from SCFTDR2
to SCTSR2, and transmission started, automatically.
SCTSR2 cannot be directly read or written to by the CPU.
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013