HD6417750RF240DV Datasheet, PDF (454/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
Bit 31—RAS Down (RASD): Sets RAS down mode. When DRAM/RAS down mode is used, set
BE to 1. Do not set RAS down mode in slave mode or partial-sharing mode, or when areas 2 and 3
are both designated as synchronous DRAM interface. See Connecting a 128-Mbit/256-Mbit
Synchronous DRAM with 64-bit Bus Width (SH7750R Only): in section 13.3.5, Synchronous
DRAM Interface.
Bit 31: RASD
Description
0
Auto-precharge mode
(Initial value)
1
RAS down mode
Note: When synchronous DRAM is used in RAS down mode, set bits DMAIW2–DMAIW0 to 000
and bits A3IW2–A3IW0 to 000.
Bit 30—Mode Register Set (MRSET): Set when a synchronous DRAM mode register setting is
used. See Power-On Sequence in section 13.3.5, Synchronous DRAM Interface.
Bit 30: MRSET
0
1
Description
All-bank precharge
Mode register setting
(Initial value)
Bits 29 to 27—RAS Precharge Time at End of Refresh (TRC2–TRC0)
(Synchronous DRAM: auto- and self-refresh both enabled; DRAM: auto- and self-refresh both
enabled)
Note: For setting values and the period during which no command is issued, see 22.3.3, Bus
Timing.
Bit 29: TRC2
0
1
Bit 28: TRC1
0
1
0
1
Bit 27: TRC0
0
1
0
1
0
1
0
1
RAS Precharge Interval
Immediately after Refresh
0
(Initial value)
3
6
9
12
15
18
21
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013