HD6417750RF240DV Datasheet, PDF (825/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 16 Serial Communication Interface with FIFO (SCIF)
SCK2/MRESET: As the manual reset pin is multiplexed with the SCK2 pin, a manual reset must
not be executed while the SCIF is operating in external clock mode.
When Using the DMAC: When using the DMAC for transmission/reception, inhibit output of
RXI and TXI interrupt requests to the interrupt controller. If interrupt request output is enabled,
interrupt requests to the interrupt controller will be cleared by the DMAC without regard to the
interrupt handler.
Serial Ports: Note that, when the SCIF pin value is read using a serial port, the value read will be
the value two peripheral clock cycles earlier.
Overrun Error Flag (SH7750): SCIF overrun error flag is not set in the case that overrun error
and flaming error occurred simultaneously in receiving data, that means 17th byte data which
overrun was accompanying with flaming error. In such case, only SCFSR2. ER flag which shows
occurrence of flaming error is set. Receive FIFO stores data received before the overrun and does
not store (i. e. lose) overrun data. SCIF has no bit which corresponds to SCFSR2. FER for the lost
data.
In addition to the overrun error handling software routine, exception handler should check co-
occurrence of overrun error when a flaming error is occurred and when a co-occurrence is found,
it should handle also overrun error (When (i) a overrun error solely occurred without
accompanying with other receive error and (ii) when a parity error is accompanied with overrun
error, usual overrun error handling can be used. Overrun error handling should rather be done
primarily).
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 773 of 1076