HD6417750RF240DV Datasheet, PDF (213/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 5 Exceptions
Table 5.3 Types of Reset
Type
Power-on reset
Manual reset
Reset State Transition
Conditions
SCK2
RESET
High
Low
Low
Low
CPU
Initialized
Initialized
Internal States
On-Chip Peripheral Modules
See Register Configuration in
each section
(3) H-UDI Reset
• Source: SDIR.TI3–TI0 = B'0110 (negation) or B'0111 (assertion)
• Transition address: H'A000 0000
• Transition operations:
Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a
branch is made to PC = H'A000 0000.
In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD,
RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK)
are set to B'1111.
CPU and on-chip peripheral module initialization is performed. For details, see the register
descriptions in the relevant sections.
H-UDI_reset()
{
EXPEVT = H'00000000;
VBR = H'00000000;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
SR.IMASK = B'1111;
SR.FD = 0;
Initialize_CPU();
Initialize_Module(PowerOn);
PC = H'A0000000;
}
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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