HD6417750RF240DV Datasheet, PDF (626/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 14 Direct Memory Access Controller (DMAC)
SH7750, SH7750S, SH7750R Group
Transfer on channel 0
Initial priority order CH0 > CH1 > CH2 > CH3
Channel 0 is given the lowest
priority.
Priority order after transfer CH1 > CH2 > CH3 > CH0
Transfer on channel 1
Initial priority order CH0 > CH1 > CH2 > CH3
Priority order after transfer ^{CH2 > CH3 > CH0 > CH1}
When channel 1 is given the
lowest priority, the priority of
channel 0, which was higher
than channel 1, is also
shifted simultaneously.
Transfer on channel 2
Initial priority order CH0 > CH1 > CH2 > CH3
When channel 2 is given the
lowest priority, the priorities of
channels 0 and 1, which were
higher than channel 2, are
also shifted simultaneously. If
there is a transfer request for
Priority order after transfer
channel 1 only immediately
CH3 > CH0 > CH1 > CH2 _{afterward, channel 1 is given}
the lowest priority and the
priorities of channels 3 and 0
are simultaneously shifted
Priority after transfer due to
down.
issuance of a transfer request ^{CH2 > CH3 > CH0 > CH1}
for channel 1 only.
Transfer on channel 3
Initial priority order _{CH0 > CH1 > CH2 > CH3}
No change in priority order
Priority order after transfer CH0 > CH1 > CH2 > CH3
Figure 14.3 Round Robin Mode
Figure 14.4 shows the changes in priority levels when transfer requests are issued simultaneously
for channels 0 and 3, and channel 1 receives a transfer request during a transfer on channel 0. The
operation of the DMAC in this case is as follows.
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013