HD6417750RF240DV Datasheet, PDF (613/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 14 Direct Memory Access Controller (DMAC)
Bits 11 to 8—Resource Select 3 to 0 (RS3–RS0): These bits specify the transfer request source.
Bit 11: Bit 10: Bit 9: Bit 8:
RS3 RS2 RS1 RS0 Description
0
0
0
0
External request, dual address mode^{*1 *4} (external address
space → external address space)
(Initial value)
1
Setting prohibited
1
0
External request, single address mode
External address space → external device^{*1 *3 *4}
1
External request, single address mode
External device → external address space^{*1 *3 *4}
1
0
0
Auto-request (external address space → external address
space)^*2
1
Auto-request (external address space → on-chip peripheral
module)^*2
1
0
Auto-request (on-chip peripheral module → external address
space)^*2
1
Setting prohibited
1
0
0
0
SCI transmit-data-empty interrupt transfer request
(external address space → SCTDR1)^*2
1
SCI receive-data-full interrupt transfer request
(SCRDR1 → external address space)^*2
1
0
SCIF transmit-data-empty interrupt transfer request
(external address space → SCFTDR2)^*2
1
SCIF receive-data-full interrupt transfer request
(SCFRDR2 → external address space)^*2
1
0
0
TMU channel 2 (input capture interrupt, external address space
→ external address space)^*2
1
TMU channel 2 (input capture interrupt, external address space
→ on-chip peripheral module)^*2
1
0
TMU channel 2 (input capture interrupt, on-chip peripheral
module → external address space)^*2
1
Setting prohibited
Notes: 1. External request specifications are valid only for channels 0 and 1. Requests are not
accepted for channels 2 and 3 in normal DMA mode.
2. Dual address mode
3. In DDT mode, selection is possible with the DTR format [60] (R/W bit) and [57-56]
(MD1, MD0 bits) specification for channel 0 only.
4. In DDT mode:
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 561 of 1076