HD6417750RF240DV Datasheet, PDF (420/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
memory control register (MCR). When the DRAM interface is used for area 2 or 3, a bus width of
16 or 32 bits should be set. For the synchronous DRAM interface, set a bus width of 32 or 64 bits
in the MCR register.
When using the PCMCIA interface, set a bus width of 8 or 16 bits.
For details, see section 13.3.7, PCMCIA Interface.
When using port functions, set a bus width of 8, 16, or 32 bits for all areas.
For details, see section 13.2.2, Bus Control Register 2 (BCR2), and section 13.2.8, Memory
Control Register (MCR).
The area 7 address range, H'1C000000 to H'1FFFFFFFF, is a reserved space and must not be used.
Note: * SH7750R only
13.1.6 PCMCIA Support
This LSI supports PCMCIA compliant interface specifications for external memory space areas 5
and 6.
The interfaces supported are the IC memory card interface and I/O card interface stipulated in
JEIDA specifications version 4.2 (PCMCIA2.1).
External memory space areas 5 and 6 support both the IC memory card interface and the I/O card
interface.
The PCMCIA interface is supported only in little-endian mode.
Table 13.4 PCMCIA Interface Features
Item
Access
Data bus
Memory type
Common memory capacity
Attribute memory capacity
Others
Features
Random access
8/16 bits
Mask ROM, OTPROM, EPROM, EEPROM, flash memory, SRAM
Max. 64 Mbytes
Max. 64 Mbytes
Dynamic bus sizing for I/O bus width, access to PCMCIA interface
from address translation areas
Page 368 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013