HD6417750RF240DV Datasheet, PDF (259/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 6 Floating-Point Unit (FPU)
Modifying a TRAP Routine: For problem types (4), (5), and (6) in table 6.3, add code to the
TRAP routine to check the instruction and input data as indicated in table 6.7 and to write the
contents of qNaN to the destination register.
In this case the value of qNaN must always be H'7FF7FFFF_FFFFFFFF.
Table 6.7 TRAP Routine Processing
Problem Type Instruction Check
(4)
FDIV
FDIV
FDIV
(5)
FADD/FSUB
FADD/FSUB
(6)
FMUL
FMUL
Input Check
DRm
DRn
qNaN
DENORM
qNaN
DENORM
DENORM
qNaN
qNaN
DENORM
DENORM
qNaN
qNaN
DENORM
DENORM
qNaN
Operation Result
qNaN
qNaN
qNaN
qNaN
qNaN
qNaN
qNaN
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 207 of 1076