HD6417750RF240DV Datasheet, PDF (159/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 3 Memory Management Unit (MMU)
31
24 23
Address field _{1 1 1 1 0 1 1 0}
14 13
87
E
A
210
31 30 29 28
Data field
VPN
10 9 8 7
0
DV
ASID
Legend:
VPN: Virtual page number
V: Validity bit
E: Entry
D: Dirty bit
ASID: Address space identifier
A: Association bit
: Reserved bits (0 write value, undefined read value)
Figure 3.16 Memory-Mapped UTLB Address Array
3.7.5 UTLB Data Array 1
UTLB data array 1 is allocated to addresses H'F700 0000 to H'F77F FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and PPN, V, SZ, PR, C, D, SH, and WT to be written to the data
array are specified in the data field.
In the address field, bits [31:23] have the value H'F70 indicating UTLB data array 1, and the entry
is selected by bits [13:8].
In the data field, PPN is indicated by bits [28:10], V by bit [8], SZ by bits [7] and [4], PR by bits
[6:5], C by bit [3], D by bit [2], SH by bit [1], and WT by bit [0].
The following two kinds of operation can be used on UTLB data array 1:
1. UTLB data array 1 read
PPN, V, SZ, PR, C, D, SH, and WT are read into the data field from the UTLB entry
corresponding to the entry set in the address field.
2. UTLB data array 1 write
PPN, V, SZ, PR, C, D, SH, and WT specified in the data field are written to the UTLB entry
corresponding to the entry set in the address field.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 107 of 1076